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28335 high resolution pulse width modulator(HRPWM)

28335 high resolution pulse width modulator(HRPWM)


TMS320x2833x, 2823x High Resolution Pulse Width Modulator

Reference Guide

Literature Number: SPRUG02 February 2009

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Contents
Preface ........................................................................................................................................ 5 1 Introduction......................................................................................................................... 9 2 Operational Description of HRPWM ...................................................................................... 10
2.1 2.2 2.3 2.4 2.5 Controlling the HRPWM Capabilities.................................................................................. 10 Configuring the HRPWM

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Principle of Operation ................................................................................................... 12 Scale Factor Optimizing Software (SFO) ............................................................................. 16 HRPWM Examples Using Optimized Assembly Code. ............................................................. 17 Register Summary ....................................................................................................... 23 Registers and Field Descriptions ...................................................................................... 24

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HRPWM Register Descriptions ............................................................................................. 23
3.1 3.2

Appendix A Revision History ...................................................................................................... 26 Appendix B SFO Library Software - SFO_TI_Build_V5.lib ............................................................... 27
B.1 B.2 SFO library Version Comparison ...................................................................................... 27 Software Usage .......................................................................................................... 30

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Table of Contents

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List of Figures
1 2 3 4 5 6 7 8 9 10 11 12 13 14 Resolution Calculations for Conventionally Generated PWM .......................................................... 9 Operating Logic Using MEP .............................................................................................. 10 HRPWM Extension Registers and Memory Configuration ............................................................ 11 HRPWM System Interface ................................................................................................ 11 Required PWM Waveform for a Requested Duty = 40.5% ........................................................... 13 Low % Duty Cycle Range Limitation Example When PWM Frequency = 1 MHz ................................. 15 High % Duty Cycle Range Limitation Example when PWM Frequency = 1 MHz ................................. 16 Simple Buck Controlled Converter Using a Single PWM ............................................................. 18 PWM Waveform Generated for Simple Buck Controlled Converter ................................................. 18 Simple Reconstruction Filter for a PWM Based DAC ................................................................. 20 PWM Waveform Generated for the PWM DAC Function ............................................................. 20 HRPWM Configuration Register (HRCNFG) ........................................................................... 24 Counter Compare A High Resolution Register (CMPAHR) ........................................................... 24 TB Phase High Resolution Register (TBPHSHR) ...................................................................... 25

List of Tables
1 2 3 4 5 6 7 8 9 A-1 B-1 B-2 B-3 Resolution for PWM and HRPWM......................................................................................... 9 HRPWM Registers ......................................................................................................... 10 Relationship Between MEP Steps, PWM Frequency and Resolution ............................................... 12 CMPA vs Duty (left), and [CMPA:CMPAHR] vs Duty (right).......................................................... 13 Duty Cycle Range Limitation for 3 and 6 SYSCLK/TBCLK Cycles .................................................. 16 Register Descriptions ...................................................................................................... 23 HRPWM Configuration Register (HRCNFG) Field Descriptions ..................................................... 24 Counter Compare A High Resolution Register (CMPAHR) Field Descriptions .................................... 24 TB Phase High Resolution Register (TBPHSHR) Field Descriptions ............................................... 25 Technical Changes in the Current Revision ............................................................................ 26 SFO library Version Comparison ......................................................................................... 27 SFO V5 Library Routines .................................................................................................. 28 Software Functions ......................................................................................................... 30

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List of Figures

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Preface
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Read This First
About This Manual
This document describes the operation of the high-resolution extension to the pulse width modulator (HRPWM). The HRPWM module described in this reference guide is a Type 0 HRPWM. See the TMS320x28xx, 28xxx DSP Peripheral Reference Guide (SPRU566) for a list of all devices with an HRPWM module of the same type, to determine the differences between types, and for a list of device-specific differences within a type.

Notational Conventions
This document uses the following conventions. ? Hexadecimal numbers are shown with the suffix h. For example, the following number is 40 hexadecimal (decimal 64): 40h. ? Registers in this document are shown in figures and described in tables. – Each register figure shows a rectangle divided into fields that represent the fields of the register. Each field is labeled with its bit name, its beginning and ending bit numbers above, and its read/write properties below. A legend explains the notation used for the properties. – Reserved bits in a register figure designate a bit that is used for future device expansion.

Related Documentation From Texas Instruments
The following documents describe the C2000? devices and related support tools. Copies of these documents are available on the Internet at www.ti.com. Tip: Enter the literature number in the search box provided at www.ti.com. The current documentation that describes the devices, related peripherals, and other technical collateral, is available in the C2000 DSP product folder at: www.ti.com/c2000. Data Manual and Errata— SPRS439— TMS320F28335, TMS320F28334, TMS320F28332, TMS320F28235, TMS320F28234, TMS320F28232 Digital Signal Controllers (DSCs) Data Manual contains the pinout, signal descriptions, as well as electrical and timing specifications for the F2833x/2823x devices. SPRZ272— TMS320F28335, F28334, F28332, TMS320F28235, F28234, F28232 Digital Signal Controllers (DSCs) Silicon Errata describes the advisories and usage notes for different versions of silicon. CPU User's Guides— SPRU430— TMS320C28x DSP CPU and Instruction Set Reference Guide describes the central processing unit (CPU) and the assembly language instructions of the TMS320C28x fixed-point digital signal processors (DSPs). It also describes emulation features available on these DSPs. SPRUEO2— TMS320C28x Floating Point Unit and Instruction Set Reference Guide describes the floating-point unit and includes the instructions for the FPU. Peripheral Guides— SPRU566— TMS320x28xx, 28xxx DSP Peripheral Reference Guide describes the peripheral reference guides of the 28x digital signal processors (DSPs). SPRUFB0— TMS320x2833x, 2823x System Control and Interrupts Reference Guide describes the various interrupts and system control features of the 2833x digital signal controllers (DSCs).

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Related Documentation From Texas Instruments

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SPRU812— TMS320x2833x, 2823x Analog-to-Digital Converter (ADC) Reference Guide describes how to configure and use the on-chip ADC module, which is a 12-bit pipelined ADC. SPRU949— TMS320x2833x, 2823x External Interface (XINTF) User's Guide describes the XINTF, which is a nonmultiplexed asynchronous bus, as it is used on the 2833x devices. SPRU963— TMS320x2833x, TMS320x2823x Boot ROM User's Guide describes the purpose and features of the bootloader (factory-programmed boot-loading software) and provides examples of code. It also describes other contents of the device on-chip boot ROM and identifies where all of the information is located within that memory. SPRUFB7— TMS320x2833x, 2823x Multichannel Buffered Serial Port (McBSP) User's Guide describes the McBSP available on the F2833x devices. The McBSPs allow direct interface between a DSP and other devices in a system. SPRUFB8— TMS320x2833x, 2823x Direct Memory Access (DMA) Reference Guide describes the DMA on the 2833x devices. SPRUG04— TMS320x2833x, 2823x Enhanced Pulse Width Modulator (ePWM) Module Reference Guide describes the main areas of the enhanced pulse width modulator that include digital motor control, switch mode power supply control, UPS (uninterruptible power supplies), and other forms of power conversion. SPRUG02— TMS320x2833x, 2823x High-Resolution Pulse Width Modulator (HRPWM) describes the operation of the high-resolution extension to the pulse width modulator (HRPWM). SPRUFG4— TMS320x2833x, 2823x Enhanced Capture (eCAP) Module Reference Guide describes the enhanced capture module. It includes the module description and registers. SPRUG05— TMS320x2833x, 2823x Enhanced Quadrature Encoder Pulse (eQEP) Reference Guide describes the eQEP module, which is used for interfacing with a linear or rotary incremental encoder to get position, direction, and speed information from a rotating machine in high performance motion and position control systems. It includes the module description and registers. SPRUEU1— TMS320x2833x, 2823x Enhanced Controller Area Network (eCAN) Reference Guide describes the eCAN that uses established protocol to communicate serially with other controllers in electrically noisy environments. SPRUFZ5— TMS320F2833x, 2823x Serial Communication Interface (SCI) Reference Guide describes the SCI, which is a two-wire asynchronous serial port, commonly known as a UART. The SCI modules support digital communications between the CPU and other asynchronous peripherals that use the standard non-return-to-zero (NRZ) format. SPRUEU3— TMS320x2833x, 2823x Serial Peripheral Interface (SPI) Reference Guide describes the SPI - a high-speed synchronous serial input/output (I/O) port - that allows a serial bit stream of programmed length (one to sixteen bits) to be shifted into and out of the device at a programmed bit-transfer rate. SPRUG03— TMS320x2833x, 2823x Inter-Integrated Circuit (I2C) Reference Guide describes the features and operation of the inter-integrated circuit (I2C) module. Tools Guides— SPRU513— TMS320C28x Assembly Language Tools User's Guide describes the assembly language tools (assembler and other tools used to develop assembly language code), assembler directives, macros, common object file format, and symbolic debugging directives for the TMS320C28x device. SPRU514— TMS320C28x Optimizing C Compiler User's Guide describes the TMS320C28x? C/C++ compiler. This compiler accepts ANSI standard C/C++ source code and produces TMS320 DSP assembly language source code for the TMS320C28x device. SPRU608— The TMS320C28x Instruction Set Simulator Technical Overview describes the simulator, available within the Code Composer Studio for TMS320C2000 IDE, that simulates the instruction set of the C28x? core.
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Related Documentation From Texas Instruments

SPRU625— TMS320C28x DSP/BIOS Application Programming Interface (API) Reference Guide describes development using DSP/BIOS.

Trademarks
C2000, TMS320C28x, C28x are trademarks of Texas Instruments.

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Reference Guide
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High-Resolution Pulse Width Modulator (HRPWM)
This document is used in conjunction with the device-specific Enhanced Pulse Width Modulator (ePWM) Module Reference Guide. The HRPWM module extends the time resolution capabilities of the conventionally derived digital pulse width modulator (PWM). HRPWM is typically used when PWM resolution falls below ~ 9-10 bits. This occurs at PWM frequencies greater than ~200 kHz when using a CPU/system clock of 100 MHz. The key features of HRPWM are: ? Extended time resolution capability ? Used in both duty cycle and phase-shift control methods ? Finer time granularity control or edge positioning using extensions to the Compare A and Phase registers ? Implemented using the A signal path of PWM, i.e., on the EPWMxA output. EPWMxB output has conventional PWM capabilities ? Self-check diagnostics software mode to check if the micro edge positioner (MEP) logic is running optimally

Topic

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Page

Table of Contents ................................................................................ 3 Preface ............................................................................................... 5 1 Introduction ............................................................................... 9 2 Operational Description of HRPWM ............................................. 10 3 HRPWM Register Descriptions ................................................... 23 Appendix A Revision History ............................................................. 26 Appendix B SFO Library Software - SFO_TI_Build_V5.lib ...................... 27

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Introduction

1

Introduction
The ePWM peripheral is used to perform a function that is mathematically equivalent to a digital-to-analog converter (DAC). As shown in Figure 1, where TSYSCLKOUT = 10 ns (i.e. 100 MHz clock), the effective resolution for conventionally generated PWM is a function of PWM frequency (or period) and system clock frequency. Figure 1. Resolution Calculations for Conventionally Generated PWM
TPWM PWM t TSYSCLK PWM resolution (%) = FPWM/FSYSCLKOUT x 100% PWM resolution (bits) = Log2 (TPWM/TSYSCLKOUT)

If the required PWM operating frequency does not offer sufficient resolution in PWM mode, you may want to consider HRPWM. As an example of improved performance offered by HRPWM, Table 1 shows resolution in bits for various PWM frequencies. Table 1 values assume a MEP step size of 180 ps. See the device-specific datasheet for typical and maximum performance specifications for the MEP. Table 1. Resolution for PWM and HRPWM
PWM Freq (kHz) 20 50 100 150 200 250 500 1000 1500 2000 Regular Resolution (PWM) Bits 12.3 11.0 10.0 9.4 9.0 8.6 7.6 6.6 6.1 5.6 % 0.0 0.0 0.1 0.2 0.2 0.3 0.5 1.0 1.5 2.0 Bits 18.1 16.8 15.8 15.2 14.8 14.4 13.8 12.4 11.9 11.4 High Resolution (HRPWM) % 0.000 0.001 0.002 0.003 0.004 0.005 0.007 0.018 0.027 0.036

Although each application may differ, typical low frequency PWM operation (below 250 kHz) may not require HRPWM. HRPWM capability is most useful for high frequency PWM requirements of power conversion topologies such as: ? Single-phase buck, boost, and flyback ? Multi-phase buck, boost, and flyback ? Phase-shifted full bridge ? Direct modulation of D-Class power amplifiers

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Operational Description of HRPWM

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2

Operational Description of HRPWM
The HRPWM is based on micro edge positioner (MEP) technology. MEP logic is capable of positioning an edge very finely by sub-dividing one coarse system clock of a conventional PWM generator. The time step accuracy is on the order of 150 ps. See the device-specific data sheet for the typical MEP step size on a particular device. The HRPWM also has a self-check software diagnostics mode to check if the MEP logic is running optimally, under all operating conditions. Details on software diagnostics and functions are in Section 2.4. Figure 2 shows the relationship between one coarse system clock and edge position in terms of MEP steps, which are controlled via an 8-bit field in the Compare A extension register (CMPAHR). Figure 2. Operating Logic Using MEP

To generate an HRPWM waveform, configure the TBM, CCM, and AQM registers as you would to generate a conventional PWM of a given frequency and polarity. The HRPWM works together with the TBM, CCM, and AQM registers to extend edge resolution, and should be configured accordingly. Although many programming combinations are possible, only a few are needed and practical. These methods are described in Section 2.5. Registers discussed but not found in this document can be seen in the device-specific Enhanced Pulse Width Modulator (ePWM) Module Reference Guide. The HRPWM operation is controlled and monitored using the following registers: Table 2. HRPWM Registers
mnemonic TBPHSHR CMPAHR HRCNFG (1)
(1)

Address Offset 0x0002 0x0008 0x0020

Shadowed No Yes No

Description Extension Register for HRPWM Phase (8 bits) Extension Register for HRPWM Duty (8 bits) HRPWM Configuration Register

This register is EALLOW protected.

2.1

Controlling the HRPWM Capabilities
The MEP of the HRPWM is controlled by two extension registers, each 8-bits wide. These two HRPWM registers are concatenated with the 16-bit TBPHS and CMPA registers used to control PWM operation. ? TBPHSHR - Time Base Phase High Resolution Register ? CMPAHR - Counter Compare A High Resolution Register

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Operational Description of HRPWM

Figure 3. HRPWM Extension Registers and Memory Configuration
0x0002 0x0003 TBPHSHR (8) Reserved (8) TBPHS (16) Single 32 bit write 31 CMPA (16) 0x0009 CMPA (16) Single 32 bit write 16 15 8 7 0 31 TBPHS (16) 16 15 8 7 0

TBPHSHR (8) Reserved (8)

0x0008

CMPAHR (8)

Reserved (8)

CMPAHR (8)

Reserved (8)

HRPWM capabilities are controlled using the Channel A PWM signal path. Figure 4 shows how the HRPWM interfaces with the 8-bit extension registers. Figure 4. HRPWM System Interface
Time?base (TB) TBPRD shadow (16) TBPRD active (16) CTR=PRD TBCTL[CNTLDE] Counter up/down (16 bit) TBCNT active (16) 16 8 Phase control CTR = PRD CTR = ZERO CTR = CMPA CTR = CMPB CTR_Dir Event trigger and interrupt (ET) EPWMxINT EPWMxSOCA EPWMxSOCB EPWMxSYNCI CTR=ZERO CTR_Dir TBPHSHR (8) TBCTL[SWFSYNC] (software forced sync) CTR=ZERO CTR=CMPB Disabled Sync in/out select Mux

EPWMxSYNCO

TBCTL[SYNCOSEL]

TBPHS active (24)

Counter compare (CC) CTR=CMPA CMPAHR (8) 16 8 CMPA active (24)

Action qualifier (AQ)

HiRes PWM (HRPWM) EPWMA EPWMxAO

CMPA shadow (24) CTR=CMPB 16 EPWMB CMPB active (16) CMPB shadow (16) CTR = ZERO Dead band (DB) PWM chopper (PC) Trip zone (TZ) EPWMxBO EPWMxTZINT TZ1 to TZ6

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Operational Description of HRPWM

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2.2

Configuring the HRPWM
Once the ePWM has been configured to provide conventional PWM of a given frequency and polarity, the HRPWM is configured by programming the HRCNFG register located at offset address 20h. This register provides configuration options for the following key operating modes: Edge Mode — The MEP can be programmed to provide precise position control on the rising edge (RE), falling edge (FE) or both edges (BE) at the same time. FE and RE are used for power topologies requiring duty cycle control, while BE is used for topologies requiring phase shifting, e.g., phase shifted full bridge. Control Mode — The MEP is programmed to be controlled either from the CMPAHR register (duty cycle control) or the TBPHSHR register (phase control). RE or FE control mode should be used with CMPAHR register. BE control mode should be used with TBPHSHR register. Shadow Mode — This mode provides the same shadowing (double buffering) option as in regular PWM mode. This option is valid only when operating from the CMPAHR register and should be chosen to be the same as the regular load option for the CMPA register. If TBPHSHR is used, then this option has no effect.

2.3

Principle of Operation
The MEP logic is capable of placing an edge in one of 255 (8 bits) discrete time steps (see device-specific data sheet for typical MEP step size). The MEP works with the TBM and CCM registers to be certain that time steps are optimally applied and that edge placement accuracy is maintained over a wide range of PWM frequencies, system clock frequencies and other operating conditions. Table 3 shows the typical range of operating frequencies supported by the HRPWM. Table 3. Relationship Between MEP Steps, PWM Frequency and Resolution
System (MHz) 50.0 60.0 70.0 80.0 90.0 100.0
(1) (2) (3) (4) (5)

MEP Steps Per SYSCLKOUT (1) (2) (3) 111 93 79 69 62 56

PWM MIN (Hz) (4) 763 916 1068 1221 1373 1526

PWM MAX (MHz) 2.50 3.00 3.50 4.00 4.50 5.00

Res. @ MAX (Bits) (5) 11.1 10.9 10.6 10.4 10.3 10.1

System frequency = SYSCLKOUT, i.e. CPU clock. TBCLK =SYSCLKOUT. Table data based on a MEP time resolution of 180 ps (this is an example value, see the device-specific data sheet for MEP limits. MEP steps applied = TSYSCLKOUT/180 ps in this example. PWM minimum frequency is based on a maximum period value, i.e. TBPRD = 65535. PWM mode is asymmetrical up-count. Resolution in bits is given for the maximum PWM frequency stated.

2.3.1

Edge Positioning In a typical power control loop (e.g., switch modes, digital motor control [DMC], uninterruptible power supply [UPS]), a digital controller (PID, 2pole/2zero, lag/lead, etc.) issues a duty command, usually expressed in a per unit or percentage terms. Assume that for a particular operating point, the demanded duty cycle is 0.405 or 40.5% on time and the required converter PWM frequency is 1.25 MHz. In conventional PWM generation with a system clock of 100 MHz, the duty cycle choices are in the vicinity of 40.5%. In Figure 5, a compare value of 32 counts (i.e. duty = 40%) is the closest to 40.5% that you can attain. This is equivalent to an edge position of 320 ns instead of the desired 324 ns. This data is shown in Table 4. By utilizing the MEP, you can achieve an edge position much closer to the desired point of 324 ns. Table 4 shows that in addition to the CMPA value, 22 steps of the MEP (CMPAHR register) will position the edge at 323.96 ns, resulting in almost zero error. In this example, it is assumed that the MEP has a step resolution of 180 ns.

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Operational Description of HRPWM

Figure 5. Required PWM Waveform for a Requested Duty = 40.5%
Tpwm = 800 ns 324 ns Demanded duty (40.5%) 10 ns steps 0 EPWM1A 30 31 32 33 34 79

37.5%

40.0%

42.5%

38.8%

41.3%

Table 4. CMPA vs Duty (left), and [CMPA:CMPAHR] vs Duty (right)
CMPA (count) (1) (2) (3) DUTY % 35.0 36.3 37.5 38.8 40.0 41.3 42.5 High Time (ns) 280 290 300 310 320 330 340 CMPA (count) 32 32 32 32 32 32 32 32 Required 32.40
(1) (2) (3)

CMPAHR (count) 18 19 20 21 22 23 24 25 26 27

Duty (%) 40.405 40.428 40.450 40.473 40.495 40.518 40.540 40.563 40.585 40.608

High Time (ns) 323.24 323.42 323.60 323.78 323.96 324.14 324.32 324.50 324.68 324.86

28 29 30 31 32 33 34

32 40.5 324 32

System clock, SYSCLKOUT and TBCLK = 100 MHz, 10 ns For a PWM Period register value of 80 counts, PWM Period = 80 x 10 ns = 800 ns, PWM frequency = 1/800 ns = 1.25 MHz Assumed MEP step size for the above example = 180 ps See the device-specific data manual for typical and maximum MEP values.

2.3.2

Scaling Considerations The mechanics of how to position an edge precisely in time has been demonstrated using the resources of the standard (CMPA) and MEP (CMPAHR) registers. In a practical application, however, it is necessary to seamlessly provide the CPU a mapping function from a per-unit (fractional) duty cycle to a final integer (non-fractional) representation that is written to the [CMPA:CMPAHR] register combination. To do this, first examine the scaling or mapping steps involved. It is common in control software to express duty cycle in a per-unit or percentage basis. This has the advantage of performing all needed math calculations without concern for the final absolute duty cycle, expressed in clock counts or high time in ns. Furthermore, it makes the code more transportable across multiple converter types running different PWM frequencies. To implement the mapping scheme, a two-step scaling procedure is required.

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Operational Description of HRPWM

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Assumptions for this example: System clock , SYSCLKOUT PWM frequency Required PWM duty cycle, PWMDuty PWM period in terms of coarse steps, PWMperiod (800 ns/10 ns) Number of MEP steps per coarse step at 180 ps (10 ns/180 ps), MEP_SF Value to keep CMPAHR within the range of 1-255 and fractional rounding constant (default value) = 10 ns (100 MHz) = 1.25 MHz (1/800 ns) = 0.405 (40.5%) = 80 = 55

= 0180h

Step 1: Percentage Integer Duty value conversion for CMPA register CMPA register value = int(PWMDuty*PWMperiod); int means integer part = int(0.405*80) = int(32.4) CMPA register value = 32 (20h)

Step 2: Fractional value conversion for CMPAHR register CMPAHR register value = (frac(PWMDuty*PWMperiod)*MEP_SF) << 8) + 0180h; frac means fractional part = (frac(32.4)*55 <<8) + 0180h; Shift is to move the value as CMPAHR high byte = ((0.4*55) << 8) + 0180h = (22<<8) + 0180h = 22*256 + 0180h ; Shifting left by 8 is the same multiplying by 256. = 5632+ 0180h = 1000h + 0180h CMPAHR value = 1780h; CMPAHR value = 1700h, lower 8 bits will be ignored by hardware.

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Operational Description of HRPWM

Note:

The MEP scale factor (MEP_SF) varies with the system clock and DSP operating conditions. TI provides an MEP scale factor optimizing (SFO) software C function, which uses the built in diagnostics in each HRPWM and returns the best scale factor for a given operating point. The scale factor varies slowly over a limited range so the optimizing C function can be run very slowly in a background loop. The CMPA and CMPAHR registers are configured in memory so that the 32-bit data capability of the 28x CPU can write this as a single concatenated value, i.e. [CMPA:CMPAHR]. The mapping scheme has been implemented in both C and assembly, as shown in Section 2.5. The actual implementation takes advantage of the 32-bit CPU architecture of the 28xx, and is somewhat different from the steps shown in Section 2.3.1. For time critical control loops where every cycle counts, the assembly version is recommended. This is a cycle optimized function (11 SYSCLKOUT cycles ) that takes a Q15 duty value as input and writes a single [CMPA:CMPAHR] value.

2.3.3

Duty Cycle Range Limitation In high resolution mode, the MEP is not active for 100% of the PWM period. It becomes operational: ? 3 SYSCLK cycles after the period starts when diagnostics are disabled ? 6 SYSCLK cycles after the period starts when SFO diagnostics are running Duty cycle range limitations are illustrated in Figure 6. This limitation imposes a lower duty cycle limit on the MEP. For example, precision edge control is not available all the way down to 0% duty cycle. Although for the first 3 or 6 cycles, the HRPWM capabilities are not available, regular PWM duty control is still fully operational down to 0% duty. In most applications this should not be an issue as the controller regulation point is usually not designed to be close to 0% duty cycle. To better understand the useable duty cycle range, see Table 5. Figure 6. Low % Duty Cycle Range Limitation Example When PWM Frequency = 1 MHz
60 ns 30 ns TPWM = 1000 ns (FPWM = 1 MHz) SYSCLKOUT = TBCLK = 100 MHz

0 EPWM1A

3

6

100

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Operational Description of HRPWM

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Table 5. Duty Cycle Range Limitation for 3 and 6 SYSCLK/TBCLK Cycles
PWM Frequency (1) (kHz) 200 400 600 800 1000 1200 1400 1600 1800 2000
(1)

3 Cycles Minimum Duty 0.6% 1.2% 1.8% 2.4% 3.0% 3.6% 4.2% 4.8% 5.4% 6.0%

6 Cycles SYSCLKOUT Minimum Duty 1.2% 2.4% 3.6% 4.8% 6.0% 7.2% 8.4% 9.6% 10.8% 12.0%

System clock - TSYSCLKOUT = 10 ns System clock = TBCLK = 100 MHz

If the application demands HRPWM operation in the low percent duty cycle region, then the HRPWM can be configured to operate in count-down mode with the rising edge position (REP) controlled by the MEP when high-resolution period is disabled (HRPCTL[HRPE] = 0). This is illustrated in Figure 7. In this case low percent duty limitation is no longer an issue. However, there will be a maximum duty limitation with same percent numbers as given in Table 5. Figure 7. High % Duty Cycle Range Limitation Example when PWM Frequency = 1 MHz
60 ns 30 ns Tpwm = 1000 ns (Fpwm = 1 MHz)

SYSCLKOUT = 100 MHz

0

3

6

100

EPWM1A

2.4

Scale Factor Optimizing Software (SFO)
The micro edge positioner (MEP) logic is capable of placing an edge in one of 255 discrete time steps. As previously mentioned, the size of these steps is on the order of 150 ps (see device-specific data sheet for typical MEP step size on your device). The MEP step size varies based on worst-case process parameters, operating temperature, and voltage. MEP step size increases with decreasing voltage and increasing temperature and decreases with increasing voltage and decreasing temperature. Applications that use the HRPWM feature should use the TI-supplied MEP scale factor optimizer (SFO) software function. The SFO function helps to dynamically determine the number of MEP steps per SYSCLKOUT period while the HRPWM is in operation. To utilize the MEP capabilities effectively during the Q15 duty to [CMPA:CMPAHR] mapping function (see Section 2.3.2), the correct value for the MEP scaling factor (MEP_SF) needs to be known by the software. To accomplish this, each HRPWM module has built in self-check and diagnostics capabilities that can be used to determine the optimum MEP_SF value for any operating condition. TI provides a C-callable library containing two SFO functions that utilize this hardware and determines the optimum MEP_SF. As such, MEP Control and Diagnostics registers are reserved for TI use.

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Operational Description of HRPWM

2.5

HRPWM Examples Using Optimized Assembly Code.
The best way to understand how to use the HRPWM capabilities is through 2 real examples: 1. Simple buck converter using asymmetrical PWM (i.e. count-up) with active high polarity. 2. DAC function using simple R+C reconstruction filter. The following examples all have Initialization/configuration code written in C. To make these easier to understand, the #defines shown below are used. Note, #defines introduced in TMS320x2833x Enhanced Pulse Width Modulator (ePWM) Module Reference Guide (literature number SPRU791) are also used. Example 1 This example assumes MEP step size of 150 ps and does not use the SFO library.

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Operational Description of HRPWM

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Example 1. #Defines for HRPWM Header Files
//-------------------------------// HRPWM (High Resolution PWM) //================================ // HRCNFG #define HR_Disable 0x0 #define HR_REP 0x1 // Rising Edge position #define HR_FEP 0x2 // Falling Edge position #define HR_BEP 0x3 // Both Edge position #define HR_CMP 0x0 // CMPAHR controlled #define HR_PHS 0x1 // TBPHSHR controlled #define HR_CTR_ZERO 0x0 // CTR = Zero event #define HR_CTR_PRD 0x1 // CTR = Period event

2.5.1 In ? ? ?

Implementing a Simple Buck Converter this example, the PWM requirements are: PWM frequency = 1 MHz (i.e., TBPRD = 100) PWM mode = asymmetrical, up-count Resolution = 12.7 bits (with a MEP step size of 150 ps)

Figure 8 and Figure 9 show the required PWM waveform. As explained previously, configuration for the ePWM1 module is almost identical to the normal case except that the appropriate MEP options need to be enabled/selected. Figure 8. Simple Buck Controlled Converter Using a Single PWM
Vin1 Buck EPWM1A Vout1

Figure 9. PWM Waveform Generated for Simple Buck Controlled Converter
Tpwrr = 1 ?s

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EPWM1A

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Operational Description of HRPWM

The example code shown consists of two main parts: ? Initialization code (executed once) ? Run time code (typically executed within an ISR) Example 2 shows the Initialization code. The first part is configured for conventional PWM. The second part sets up the HRPWM resources. This example assumes MEP step size of 150 ps and does not use the SFO library. Example 2. HRPWM Buck Converter Initialization Code
void HrBuckDrvCnf(void) { // Config for conventional PWM first EPwm1Regs.TBCTL.bit.PRDLD = TB_IMMEDIATE; // set Immediate load EPwm1Regs.TBPRD = 100; // Period set for 1000 kHz PWM hrbuck_period = 200; // 2 x Period, for Q15 to Q0 scaling EPwm1Regs.TBCTL.bit.CTRMODE = TB_COUNT_UP; EPwm1Regs.TBCTL.bit.PHSEN = TB_DISABLE; // EPWM1 is the Master EPwm1Regs.TBCTL.bit.SYNCOSEL = TB_SYNC_DISABLE; EPwm1Regs.TBCTL.bit.SYNCOSEL = TB_SYNC_DISABLE; EPwm1Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1; EPwm1Regs.TBCTL.bit.CLKDIV = TB_DIV1; // Note: ChB is initialized here only for comparison purposes, it is not required EPwm1Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO; EPwm1Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW; EPwm1Regs.CMPCTL.bit.LOADBMODE = CC_CTR_ZERO; // optional EPwm1Regs.CMPCTL.bit.SHDWBMODE = CC_SHADOW; // optional EPwm1Regs.AQCTLA.bit.ZRO = AQ_SET; EPwm1Regs.AQCTLA.bit.CAU = AQ_CLEAR; EPwm1Regs.AQCTLB.bit.ZRO = AQ_SET; // optional EPwm1Regs.AQCTLB.bit.CBU = AQ_CLEAR; // optional // Now configure the HRPWM resources EALLOW; // Note these registers are protected // and act only on ChA EPwm1Regs.HRCNFG.all = 0x0; // clear all bits first EPwm1Regs.HRCNFG.bit.EDGMODE = HR_FEP; // Control Falling Edge Position EPwm1Regs.HRCNFG.bit.CTLMODE = HR_CMP; // CMPAHR controls the MEP EPwm1Regs.HRCNFG.bit.HRLOAD = HR_CTR_ZERO; // Shadow load on CTR=Zero EDIS; MEP_SF = 66*256; // Start with typical Scale Factor //value for 100 MHz // Note: Use SFO functions to update MEP_SF dynamically }

Example 3 shows an assembly example of run-time code for the HRPWM buck converter. Example 3. HRPWM Buck Converter Run-Time Code
EPWM1_BASE .set 0x6800 CMPAHR1 .set EPWM1_BASE+0x8 ;=============================================== HRBUCK_DRV; (can execute within an ISR or loop) ;=============================================== MOVW DP, #_HRBUCK_In MOVL XAR2,@_HRBUCK_In ; Pointer to Input Q15 Duty (XAR2) MOVL XAR3,#CMPAHR1 ; Pointer to HRPWM CMPA reg (XAR3) ; Output for EPWM1A (HRPWM) MOV T,*XAR2 ; T <= Duty MPYU ACC,T,@_hrbuck_period ; Q15 to Q0 scaling based on Period MOV T,@_MEP_SF ; MEP scale factor (from optimizer s/w) MPYU P,T,@AL ; P <= T * AL, Optimizer scaling MOVH @AL,P ; AL <= P, move result back to ACC ADD ACC, #0x180 ; MEP range and rounding adjustment MOVL *XAR3,ACC ; CMPA:CMPAHR(31:8) <= ACC ; Output for EPWM1B (Regular Res) Optional - for comparison purpose only MOV *+XAR3[2],AH ; Store ACCH to regular CMPB

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Operational Description of HRPWM

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2.5.2 In ? ? ?

Implementing a DAC function Using an R+C Reconstruction Filter this example, the PWM requirements are: PWM frequency = 400 kHz (i.e. TBPRD = 250) PWM mode = Asymmetrical, Up-count Resolution = 14 bits ( MEP step size = 150 ps)

Figure 10 and Figure 11 show the DAC function and the required PWM waveform. As explained previously, configuration for the ePWM1 module is almost identical to the normal case except that the appropriate MEP options need to be enabled/selected. Figure 10. Simple Reconstruction Filter for a PWM Based DAC
EPWM1A LPF VOUT1

Figure 11. PWM Waveform Generated for the PWM DAC Function
TPWM = 2.5 ?S

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The example code shown consists of two main parts: ? Initialization code (executed once) ? Run time code (typically executed within an ISR) This example assumes a typical MEP_SP and does not use the SFO library. Example 4 shows the Initialization code. The first part is configured for conventional PWM. The second part sets up the HRPWM resources.

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Operational Description of HRPWM

Example 4. PWM DAC Function Initialization Code
void HrPwmDacDrvCnf(void) { // Config for conventional PWM first EPwm1Regs.TBCTL.bit.PRDLD = TB_IMMEDIATE; EPwm1Regs.TBPRD = 250; hrDAC_period = 250; // Set Immediate load // Period set for 400 kHz PWM // Used for Q15 to Q0 scaling

EPwm1Regs.TBCTL.bit.CTRMODE = TB_COUNT_UP; EPwm1Regs.TBCTL.bit.PHSEN = TB_DISABLE; // EPWM1 is the Master EPwm1Regs.TBCTL.bit.SYNCOSEL = TB_SYNC_DISABLE; EPwm1Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1; EPwm1Regs.TBCTL.bit.CLKDIV = TB_DIV1; // Note: ChB is initialized here only for comparison purposes, it is not required EPwm1Regs.CMPCTL.bit.LOADAMODE EPwm1Regs.CMPCTL.bit.SHDWAMODE EPwm1Regs.CMPCTL.bit.LOADBMODE EPwm1Regs.CMPCTL.bit.SHDWBMODE = = = = CC_CTR_ZERO; CC_SHADOW; CC_CTR_ZERO; CC_SHADOW;

// optional // optional

EPwm1Regs.AQCTLA.bit.ZRO = AQ_SET; EPwm1Regs.AQCTLA.bit.CAU = AQ_CLEAR; EPwm1Regs.AQCTLB.bit.ZRO = AQ_SET; EPwm1Regs.AQCTLB.bit.CBU = AQ_CLEAR; // Now configure the HRPWM resources EALLOW; EPwm1Regs.HRCNFG.all = 0x0; EPwm1Regs.HRCNFG.bit.EDGMODE = HR_FEP; EPwm1Regs.HRCNFG.bit.CTLMODE = HR_CMP; EPwm1Regs.HRCNFG.bit.HRLOAD = HR_CTR_ZERO; EDIS; MEP_SF = 66*256;

// optional // optional

// // // // // // // // // //

Note these registers are protected and act only on ChA. Clear all bits first Control falling edge position CMPAHR controls the MEP. Shadow load on CTR=Zero. Start with typical Scale Factor value for 100 MHz. Use SFO functions to update MEP_SF dynamically.

}

Example 5 shows an assembly example of run-time code that can execute in a high-speed ISR loop.

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Operational Description of HRPWM

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Example 5. PWM DAC Function Run-Time Code
EPWM1_BASE CMPAHR1 .set .set 0x6800 EPWM1_BASE+0x8

;================================================= HRPWM_DAC_DRV; (can execute within an ISR or loop) ;================================================= MOVW DP, #_HRDAC_In MOVL XAR2,@_HRDAC_In ; Pointer to input Q15 duty (XAR2) MOVL XAR3,#CMPAHR1 ; Pointer to HRPWM CMPA reg (XAR3) ; Output for EPWM1A (HRPWM) MOV T,*XAR2 MPY ACC,T,@_hrDAC_period ADD ACC,@_HrDAC_period<<15 MOV T,@_MEP_SF MPYU P,T,@AL MOVH @AL,P ADD ACC, #0x180 MOVL *XAR3,ACC

; ; ; ; ; ; ; ;

T <= duty Q15 to Q0 scaling based on period Offset for bipolar operation MEP scale factor (from optimizer s/w) P <= T * AL, optimizer scaling AL <= P, move result back to ACC MEP range and rounding adjustment CMPA:CMPAHR(31:8) <= ACC

; Output for EPWM1B (Regular Res) Optional - for comparison purpose only MOV *+XAR3[2],AH ; Store ACCH to regular CMPB

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HRPWM Register Descriptions

3

HRPWM Register Descriptions
This section describes the applicable HRPWM registers

3.1

Register Summary
A summary of the registers required for the HRPWM is shown in Table 6. Table 6. Register Descriptions

Name Time Base Registers TBCTL TBSTS TBPHSHR TBPHS TBCNT TBPRD Reserved Compare Registers CMPCTL CMPAHR CMPA CMPB EPWM Registers ePWM HRCNFG Reserved

Offset 0x0000 0x0001 TBPHSHR 0x0003 0x0004 0x0005 0x0006 0x0007 0x0008 0x0009 0x000A 0x0000 to 0x001F 0x0020 0x0030 0x003F

Size (x16) 1/0 1/0 1/0 1/0 1/0 1/1 1/0 1/0 1/1 1/1 1/1 32 1 16

Description Time Base Control Register Time Base Status Register Time Base Phase High Resolution Register Time Base Phase Register Time Base Counter Register Time Base Period Register Set [3]

Counter Compare Control Register Counter Compare A High Resolution Register Set Counter Compare A Register Set Counter Compare B Register Set [4] Other ePWM registers including the ones given above. HRPWM Configuration Register

EPWM/HRPWM Test Registers

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HRPWM Register Descriptions

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3.2

Registers and Field Descriptions
Figure 12. HRPWM Configuration Register (HRCNFG)
15 Reserved R-0 8

7 Reserved R-0

4

3 HRLOAD R/W-0

2 CTLMODE R/W-0

1 EDGMODE R/W-0

0

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 7. HRPWM Configuration Register (HRCNFG) Field Descriptions
Bit 15-4 3 Field Reserved HRLOAD 0 1 Value Description (1) Reserved Shadow mode bit: Selects the time event that loads the CMPAHR shadow value into the active register: CTR = zero (counter equal zero) CTR=PRD (counter equal period) Note: Load mode selection is valid only if CTLMODE=0 has been selected (bit 2). You should select this event to match the selection of the CMPA load mode ( i.e., CMPCTL[LOADMODE] bits) in the EPWM module as follows: 00 01 10 11 2 CTLMODE 0 1 1-0 EDGMODE 00 01 10 11
(1)

Load on CTR = Zero: Time-base counter equal to zero (TBCTR = 0x0000) Load on CTR = PRD: Time-base counter equal to period (TBCTR = TBPRD) Load on either CTR = Zero or CTR = PRD (should not be used with HRPWM) Freeze (no loads possible – should not be used with HRPWM)

Control Mode Bits: Selects the register (CMP or TBPHS) that controls the MEP: CMPAHR(8) Register controls the edge position ( i.e., this is duty control mode). (default on reset) TBPHSHR(8) Register controls the edge position ( i.e., this is phase control mode). Edge Mode Bits: Selects the edge of the PWM that is controlled by the micro-edge position (MEP) logic: HRPWM capability is disabled (default on reset) MEP control of rising edge MEP control of falling edge MEP control of both edges

This register is EALLOW protected.

Figure 13. Counter Compare A High Resolution Register (CMPAHR)
15 CMPAHR R/W-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset 8 7 Reserved R/W-0 0

Table 8. Counter Compare A High Resolution Register (CMPAHR) Field Descriptions
Bit 15-8 7-0 Field CMPAHR Reserved Value Description Compare A High Resolution register bits for MEP step control. A minimum value of 0x0001 is needed to enable HRPWM capabilities. Valid MEP range of operation 1-255h.

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HRPWM Register Descriptions

Figure 14. TB Phase High Resolution Register (TBPHSHR)
15 TBPHSH R/W-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset 8 7 Reserved R/W-0 0

Table 9. TB Phase High Resolution Register (TBPHSHR) Field Descriptions
Bit 15-8 7-0 Field TBPHSH Reserved Value Description Time base phase high resolution bits

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Appendix A

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Appendix A Revision History
This document was revised to SPRUG02A from SPRUG02. This appendix lists only revisions made in the most recent version. The scope of the revisions was limited to technical changes as shown in Table A-1. Table A-1. Technical Changes in the Current Revision
Location Global Table 4 Table 5 Additions, Deletions, Modifications Replaced Map with Mep Revised table note. Revised table note and one value.

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Revision History

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Appendix B

Appendix B SFO Library Software - SFO_TI_Build_V5.lib
This appendix includes a detailed description of the software routines in SFO_TI_Build_V5.lib which supports up to 16 HRPWM channels.

B.1

SFO library Version Comparison
Table B-1 includes a high-level comparison between SFO_TI_Build.lib and SFO_TI_V5.lib. A detailed description of SFO_TI_Build_V5.lib follows the table, and more information on SFO_TI_Build.lib can be found in Section 2.4. Table B-1. SFO library Version Comparison
SYSCLK Freq Max. HRPWM channels supported Total static variable memory size MepEn runs on multiple channels concurrently? Error-checking? Typical time requires for MepEn to update MEP_ScaleFactor on 1 channel if called repetitvely without interrupts Typical time required for MepDis to update MEP_ScaleFactor on 1 channel if called repetitively without interrupts 100MHz 60MHz 50MHz ePWM Freq 3.33 MHz 400 kHz 1 MHz 2 MHz 20 MHz SFO_TI_Build.lib Up to 4 220 yes no 0.396 3.26 1.308 0.66 0.066 0.83 1.38 1.66 SFO_TI_Build_V5.lib Up to 16 79(1 ch.) to 192 (16ch.) no yes 0.18 1.5 0.6 0.3 0.03 0.83 1.38 1.66 Unit channels words seconds seconds seconds seconds seconds milliseconds milliseconds milliseconds

In SFO_TI_Build_V5.lib, the diagnostic software has been optimized to use less memory, to minimize the calibration time, and to support up to 16 HRPWM channels. Table B-2 provides functional description of the two SFO library routines in SFO_TI_Build_V5.lib.
Note: For the F2833x floating point devices, when compiling application code for floating point (fpu32 mode), libraries utilized by the application code must also be compiled for floating point. The SFO_TI_Build_fpu.lib and SFO_TI_Build_V5_fpu.lib are available as the floating point compiled equivalents to the fixed point SFO_TI_Build.lib and SFO_TI_Build_V5.lib libraries. The SFO functions in the fpu-version libraries are C-code-compatible to their fixed-point equivalents.

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SFO library Version Comparison

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Table B-2. SFO V5 Library Routines
Function int SFO_MepDis_V5(n) Description Scale Factor Optimizer V5 with MEP Disabled This routine is very similar to the SFO_MepDis() routine in the original SFO library, but with one change. It now returns a 1 when MEP-disabled calibration is complete, or a 0 while calibration is still running. This function runs faster than the SFO_V5() routine and cannot be used on an ePWM channel while HRPWM capablities are enabled for that channel. If there is a spare ePWM channel available in the system. SFO_MepDis_V5() can be run for that channel, and the resulting MEP_ScaleFactor[n] value can be copied into the MEP_ScaleFactor[n] for all other channels. If SYSCLKOUT = TBCLK =100 MHz and assuming the MEP step size is 150 ps: Typical value at 100 MHz = 66 MEP steps per unit TBCLK (10 ns) The funtion returns a value in the variable array: MEP_ScaleFactor[n] Number of MEP steps/SYSCLKOUT If TBCLK is not equal to SYSCLKOUT, then the returned value must be adjusted to reflect the correct TBCLK: MEP steps per TBCLKK =MEP_ScaleFactor[n] * (SYSCLKOUT/TBCLK) Example: If TBCLK = SYSCLKOUT/2, MEP steps per TBCLK = MEP_ScaleFactor[n] * (100/50) = 66 *2 = 132 Constraints when using this function: ? SFO_MepDis_V5(n) can be used with SYSCLKOUT from 50 MHz to 100 MHz (or maximum SYSCLK frequency). MEP diagnostics logic uses SYSCLKOUT and not TBCLK. Hence, the SYSCLKOUT restriction is an important constraint. ? If TBCLK does not equal SYSCLKOUT, the TBCLK frequency must be great enough so that MEP steps per TBCLK do not exceed 255. This is due to the restriction that there can be no more than 255 MEP steps in a coarse step. ? This function cannot be run on an ePWM channel with HRPWM capabilities enabled. Running the SFP_MepDis_V5 function continuously in an application will generate an inaccurate waveform on the HRPWM channel output pin. Usage: ? If one of the ePWM modules is running in normal ePWM mode, then it can be used to run the SFO diagnostics function. Here, the single MEP_ScaleFactor value obtained for that channel can be copied and used as the MEP_ScaleFactor for the other ePWM modules which are running HRPWM modules' MEP steps are similar but may not be identical. ? This routine returns a 1 when calibration is finished on the specified channel or a 0 if calibration is still running. ? The ePWM module that is not active in HRPWM mode is still fully operational in conventional PWM mode and used to drive PWM pins. The SFO function only makes ise of the MEP diagnostics logic in the HRPWM circuitry. ? SFO_MepDis_V5(n) function does not require a starting Scale Factor value. ? The other ePWM modules operating in HRPWM mode incur only a 3-cycle minimum duty cycle limitation. int SFO_MepEn_V5(n) Scale Factor Optimizer V5 with MEP Enabled This function runs slower that the SFO_MepDis_V5() routine and runs SFO diagnostics on an ePWM channel with HRPWM capabilities enabled for that channel. If SYSCLK = TBCLK = 100MHz, and assuming MEP step size is 150 ps: Typical value at 100 MHz = 66 MEP steps per unit TBCLK (10 ns) The function returns a value in the variable array: MEP_ScaleFactor(n) =Number of MEP steps/SYSCLKOUT =Number of MEP steps/TBCLK

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SFO library Version Comparison

Table B-2. SFO V5 Library Routines (continued)
Function Description Constraints when using this function: ? This routine must be run on one channel at a time and cannot be run on multiple channels concurrently. When it has finished updating the MEP_ScaleFactor for a channel, it will return a 1. If it is still calibrating, it will return a 0. A background loop should exist in the ISR code which calls SFO_MepEn_V5(n) repeatedly until it returns a 1. Then the function can be called for the next channel. (1)

Note:

Unlike the original SFO_MepEn(n) routine, this routine cannot run on multiple channels concurrently. Do not call SFO_MepEn_V5(n) for another channel until the function returns a 1 for the current channel. Otherwise, the MEP_ScaleFactor for both channels will become corrupted.

Note:

SFO_MepEn_V5(n) in SFO_TI_Build_V5.lib supports only the following HRPWM configuration:
? HRCNFG[HRLOAD] = 0 (load on CTR = ZERO) ? HRCNFG[EDGMODE] = 10(falling edge MEP control)

An upgraded version of SFO_MepEn_V5(n) in SFO_TI_Build_V5B.lib supports all available HRPWM configurations. When using this version, the HRCNFG register must be initialized with the appropriate configuration after calling SFO_MepDis_V5(n) to seed the MEP_ScaleFactor[n] and prior to calling SFO_MepEn_V5(n).
? The SFO_MepEn_V5(n) function requires a SYSCLKOUT between 60 MHz and 100 MHz (or maximum SYSCLK frequency) only. MEP diagnostics logic uses SYSCLKOUT and not TBCLK. Hence the SYSCLKOUT restriction is an important constraint. Usage: ? After calling SFO_MepDis(n) to seed MEP_ScaleFactor[n], and prior to using the SFO_MepEn(n) function in SPO_TI_Build_V5B.lib, the HRCNFG register must be initialized with the desired HRPWM configuration. Otherwise, calibration will not be initiated, and calls to SFO_MepEn_V5(n) will continuously return 0. ? The SFO_MepEn_V5(n) function requires a starting scale factor value, MEP_ScaleFactor[0]. MEP_ScaleFactor[0] needs to be initialized to a typical MEP step size value. To do this, SFO_MepDis_V5(n) can be run on an ePWM channel while the HRPWM is disabled, and the resulting MEP_ScaleFactor[n] value can be copied into MEP_ScaleFactor[0]. ? If there are drastic environmental changes to your system (i.e. temperature/voltage), it is generally a good idea to re-seed MEP_ScaleFactor[0] with a new typical MEP step size value for the changed conditions. ? Because SFO_MepEn_V5(n) can be run on only one channel at a time, it is only recommended for systems where there are no spare HRPWM channels available, so SFO calibration must be performed on all channels with HRPWM capabilities enabled. In this case, a 6-cycle MEP inactivity zone exists at the start of each PWM period on all HRPWM channels. See Section 2.3.3 on duty cycle range limitations. ? The function returns: – A one when it has finished SFO calibration for the current channel – A zero when SFO diagnostics are still running for the channel – A two as an error indicator after calibration has completed if the resulting MEP_ScaleFactor for the channel differs from the original MEP_ScaleFactor[0] seed value by more than +/- 15 The function must be called repetitively before it will return a 1. This function takes a longer time to complete than the SFO_MepDis_V5(n) calibration.

(1)

If SFO calibration must be run on multiple channels at a time while HRPWM capabilities are enabled, the previous version of the SFO library, SFO_TI_Build.lib, which uses more memory resources, can be used instead, and SFO_MepEn(n) can run concurrently for up to 4 ePWM channels with HRPWM enabled.

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Software Usage

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Table B-2. SFO V5 Library Routines (continued)
Function Description If it returns a 2, the MEP_ScaleFactor for the channel has finished updating and is outside the typical drift range of MEP_ScaleFactor[0] +/- 15 even with large temperature and voltage variations. If the reason for large difference between the seed and the channel scale factor is known and acceptable, the user may choose to ignore the return value of 2, and treat it as a return value of 1, indicating that calibration is complete. Otherwise, if the large difference is unexpected, there are steps to take to remedy the error: 1. Check your code to ensure SFO_MepEn_V5(n) is not being called on more than one channel at a time. 2. If the above is not effective, run SFO_MepDis_V5(n) again and re-seed Mep_ScaleFactor[0]. 3. If neither of the above 2 steps work, there may be a system problem. The application firmware should perform shutdown or an appropriate recovery procedure. ? If all ePWM modules are using the same TBCLK prescalers, then it is possible to run the SFO_MepEn_V5(n) function for only one ePWM module and to use the MEP_ScaleFactor value for that module for the other modules also. In this case only one ePWM module incurs the 6-cycle duty limitation, and the remaining modules incur only a 3-cycle minimum duty limitation. This assumes that all HRPWM modules' MEP steps are similar but may not be identical.

B.2

Software Usage
Software library functions int SFO_MepEn_V5(int n) and int SFO_MepDis_V5(int n) calculate the MEP scale factor for ePWMn Modules, where n= the ePWM channel number. The scale factor value, which represents the number of micro-steps availablein a system clock period, is returned in a global array of integer values called MEP_ScaleFactor[x], where x is he maximum numver of HRPWM channels for a device plus one. For example, if the maximum number of HRPWM channels for a device is 16, the scale factor array would be MEP_ScaleFactor[17]. Both SFO_MepEn_V5 and SFO_MepDis_V5 themselves also return a 1 when calibration has completed, indicating the MEP_ScaleFactor has been successfully updated for the channel, and a 0 when calibration is still on-going. A return of 2 represents an out-of-range error. Table B-3. Software Functions
Software functional calls int SFO_MepDis_V5(int n) status = SFO_MepDis_V5(1) status = SFO_MepDis_V5(2) ... status = SFO_MepDis_V5(16) int SFO_MepEn_V5(int n) status = SFO_MepEn_V5(1) status = SFO_MepEn_V5(2) ... status = SFO_MepEn_V5(16) The scale factor in MEP_ScaleFactor[1] updated when status = 1 or 2. The scale factor in MEP_ScaleFactor[2] updated when status = 1 or 2. ... The scale factor in MEP_ScaleFactor[16] updated when status = 1 or 2. The scale factor in MEP_ScaleFactor[1] updated when status = 1. The scale factor in MEP_ScaleFactor[2] updated when status = 1. ... The scale factor in MEP_ScaleFactor[16] updated when status = 1 or 2. Functional Description

To use the HRPWM feature of the ePWMs, it is recommended that the SFO functions in TI_Build_V5.lib be used as described here. The examples below are specific to the TMS320F28044 device, which includes a maximum of 16 HRPWM channels. For different devices which may have fewer HRPWM channels, modifications will be required in Step 1 and Step 2 below.

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Software Usage

Step 1. Add "Include" Files The SFO_V5.h file needs to be included as follows. This include file is mandatory when using the SFO V5 library functions. For the TMS320F28044 device, the C2804x C/C++ Header Files and Peripheral Examples (literature number SPRC324) DSP2804x_Device.h and DSP2804x_PWM_defines.h files are necessary as will, as they are used by all TI software examples for the device. These file names will change in accordance with your specific device. These include files are optional if customized header files are used in the end application. See example below. Example 1. A Sample of How to Add "Include" Files
#include "DSP2804x_Device.h" #include "DSP2804x_EPWM_defines.h" #include "SFO_V5.h" //DSP2804x Headerfile //init defines //SFO V5 lib functions (needed for HRPWM)

Step 2. Define Number of HRPWM Channels Used In the SFO_V5.h file, the maximum number of HRPWM's used for a peticular device must be defines. PWM_CH must equal the number of HRPWM channels plus one. For instance, for the TMS320F28044 where there are 16 possible HRPWM channels, PWM_CH can be set to 17. For the TMS320F2809, where there are 6 possible HRPWM channnels, PWM_CH can be set to 7. See example below. To save static variable memory, fewer than the maximum number of HRPWM channels may be defined with some caution. To do this, PWM_CH can be set to the largest ePWM channel number plus one. For instance, if only ePWM1A and ePWM2A channels are required as HRPWM channels, PWM_CH can be set to 3. However, if only ePWM15A and ePWM16A channels are required as HRPWM channels, PWM_CH must still be set to 17. Example 2. Defining Number of HRPWM Channels Used (Plus One)
//SFO_V5.H //NOTE: THIS IS A VERY IMPORTANT STEP> PWM_CH MUST BE DEFINED FIRST BEFORE //BUILDING CODE #define PWM_CH 17 //F28044 has a //For a device //For a device //For a device maximum of 16 HRPWM channels (17=16+1) with maximum of 6 HRPWM channels, PWM_CH = 7 with maximum of 4 HRPWM channels, PWM_CH = 5 with maximum of 3 HRPWM channels, PWM_CH = 4

Step 3. Element Declaration Declare an array of integer variables with a length equal to PWM_CH, and an array of pointers to EPWM register structures. The array of pointers will include pointers for up to 16 EPWM register structures plus one dummy pointer in location EPWM[0] for a device with 16 EPWM channels. Likewise, it will include pointers for up to 3 EPWM register structures plus one for a device with 3 EPWM registers. Example 3. Declaring Elements Required by SFO_TI_Build_V5.lib
int MEP_ScaleFactor[PWM_Ch] = {0,0,0,0,0, 0,0,0,0, 0,0,0,0, 0,0,0,0}; //Scale factor values for ePWM 1-16 //and MEP_ScaleFactor[0] //For Fewer HRPWM channels, these //will be fewer zeros initialized

//Declare a volatile array of pointers to EPWM register structures. //Only point to registers that exist. If a device has only 6 EPWMs (PWM_CH is 7), //the array will include pointers for up to 6 EPWM register structures plus one //dummy pointer in the ePWM[0] location. volatile struct EPWM_REGS *ePWM[PWM_CH] {&EPwm1Regs, &EPwm1Regs &EPwm2Regs, &EPwm3Regs, &EPwm4Regs, &EPwm5Regs, &EPwm6Regs, &EPwm7Regs, &EPwm8Regs, &EPwm9Regs, &EPwm10Regs, &EPwm11Regs, &EPwm12Regs, &EPwm13Regs, &EPwm14Regs, &EPwm15Regs, &EPwm16Regs};

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Software Usage

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Step 4. MEP_ScaleFactor After power up, the SFO_MepEn_V5(n) function needs a typical scale factor starting seed value in MEP_ScaleFacter[0]. This value can be conveniently determined using one of the ePWM modules to run the SFO_MepDis_V5(n) function prior to initializing the PWM settings for the application. The SFO_MepDis_V5(n) function does not require a starting scale factor value. As part of the one-time initialization code prior to using MEP_SF, include the following: Example 4. Initializing With a Scale Factor Value
//MEP_ScaleFactor varaibles initialized using function SFO_MepDis_V5 Uint16 i; for(i=1; i<PWM_CH; i++) //for channels 1-16 { While (SFO_MepDis_V5(i) == 0); //Calls MepDis unitl MEP_ScaleFactor updated } //initialize MEP_ScaleFactor[0] with a typical MEP seed value //required for SFO_MepEn_V5 MEP_ScaleFactor[0] = MEP_ScaleFactor[1];

Step 5. Application Code While the application is running, fluctuations in both device temperature and supply voltage may be expected. To be sure that optimal scalee factors are used for each ePWM modules, the SFO function should be re-run periodically as part of a slower background loop. Some examples of this are shown here in the below example. Example 5. SFO Function Calls
main() { Uint16 current_ch = 1; Uint16 status; //user code //Case 1: all ePWMs are running in HRPWM mode // here, the minimum duty cycle limitation is 6 clock cycles status = SFO_MepEn_V5(current_ch); if(status == 1) { current_ch++; } else if( status == 2) { error(); } if(current_ch == PWM_CH) { current_ch=1; } //MepEn called here //if MEP_ScaleFactor has been updated //move on to the next channel //if MEP_ScaleFactor differs from //MEP_ScaleFactor[0] seed by more than //+/-15, flag an error //if last channel has been reached //go back to channel 1

//keeps track of current HRPWM channel being calibrated

//Case 2: All ePWMs except one are running in HRPWM mode. // One of the ePWM channels (ePWM16 in this example is used // for SFO_MepDis_V5 scale factor calibration. // Here, the minimum duty cycle limitation is 3 clock cycles. // // // HRPWM diagnostics circuitry is used to estimate the MEP steps with the assumption that all HRPWM channels behave similarly though they may not be identical while( SFO_MepDis_V5(16) == 0); //wait until MEP_ScaleFactor[16] updates for(i=1; i<(PWM_CH-1); i++) //update scale factors for ePWM 1-15 { MEP_ScaleFactor[i] = MEP_ScaleFactor[16]; }

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Software Usage Note: See the hrpwm_sfo_v5 example in your device-specific Header Files and Peripheral Examples software package availableon the TI website.

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